Verilog & FPGA Design Expert (Vivado)

Course Description
‘Verilog & FPGA Design’ is a comprehensive training package that comprises of 2 course modules: Designing with Verilog and Essentials of FPGA. Based on Xilinx industry standard, this 6-day training package can be considered as the minimum training requirement for project readiness.

Designing with Verilog (3-day) This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001. You will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Essentials of FPGA Design (2-day) is specially designed for designers new to FPGAs design or programmable logic. Build an effective FPGA design using synchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.

Hands-on Project (1-day) on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.

Who Should Attend
Digital designers who are interested in FPGA design training and want to use Verilog effectively for modeling, design, and synthesis of digital designs and learn to use Xilinx FPGAs.

6 days


  • Basic digital design knowledge

Skills Gained
After completing this training, you will be able to:

Design with Verilog

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a Finite State Machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capability
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the Vivado™ Design Suite environment
  • Download to the evaluation demo board

Essentials of FPGA

  • Take advantage of the primary 7 series FPGA architecture resources
  • Use the Project Manager to start a new project
  • Identify the available Vivado IDE design flows (project based and non-project batch)
  • Identify file sets (HDL, XDC, simulation)
  • Analyze designs by using the cross-selection capabilities, Schematic viewer, and Hierarchical viewer
  • Synthesize and implement an HDL design
  • Utilize the available synthesis and implementation reports to analyze a design (utilization, timing, power, etc.)
  • Build custom IP with the IP Library utility
  • Make basic timing constraints (create_clock, set_input_delay, and set_output_delay)
  • Use the primary Tcl-based reports (check_timing, report_clock_interaction, report_clock_networks, and report_timing_summary)
  • Describe and analyze common STA reports
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline

Module 1: Designing with Verilog

Day 1

1.1 Introduction to Verilog
1.2 Verilog Keywords and Identifiers
1.3 Verilog Data Types
1.4 Verilog Buses and Arrays
1.5 Verilog Modules and Ports
1.6 Demo: Multiplexer
1.7 Lab 1: Building Hierarchy
1.8 Verilog Operators
1.9 Continuous Assignment
1.10  Gate-Level Modeling
1.11 Procedural Assignment
1.12 Blocking and Non-Blocking Procedural Assignment
1.13 Lab 2: Creating a Simple Memory
1.14 Procedural Timing Control

Day 2

2.1 Verilog Conditional Statements: if_else
2.2 Lab 3: Building the Clock Divider and Address Counter
2.3 Verilog Conditional Statements: case
2.4 Verilog Loop Statements
2.5 Introduction to Verilog Testbenches
2.6  Lab 4: Verilog Simulation and RTL Verification
2.7 System Tasks
2.8 Verilog Sub-Programs
2.9 Verilog Functions
2.10 Verilog Tasks
2.11 Verilog Compiler Directives
2.12 Parameter Concept
2.13 Lab 5: Creating an n-bit Binary Counter
2.14  Generate Statement

Day 3

3.1 Verilog Timing Checks
3.2 Finite State Machine
3.3 Finite State Machine: Mealy
3.4 Lab 6: Building a Mealy Finite State Machine
3.5 Finite State Machine: Moore
3.6 Lab 7: Building a Moore Finite State Machine
3.7 FSM Coding Guidelines
3.8 File I/O Introduction
3.9 File I/O Read Functions
3.10  Lab 8: Using Verilog File I/O
3.11 File I/O Write Functions
3.12 Targeting Xilinx FPGAs
3.13 Lab 9: Implementing and Downloading the Design
3.14 User-Defined Primitives
3.15 Programming Language Interface

Module 2: FPGA Design Expert

Day 4

  • Design Methodology Summary
  • Basic FPGA Architecture
  • Vivado IDE Features and Benefits
  • Introduction to the Vivado Design Suite
  • Vivado IDE Project Manager and IP Library
  • Vivado IDE Tool Overview
  • Lab 1: Vivado Tool Overview
  • Vivado IDE Synthesis and Reports
  • Vivado IDE Implementation and Static Timing Analysis
  • Lab 2: Vivado Synthesis and Implementation

Day 5

  • Designing with FPGA Resources
  • Clocking Resources
  • Lab 3a: Designing with FPGA Resources
  • Lab 3b: Creating an IP Integrator Subsystem Design
  • Basic Timing Constraints (XDC)
  • Timing Reports
  • Lab 4: Basic XDC and Timing Reports
  • Synchronous Design Techniques
  • FPGA Configuration
  • Appendix: SystemVerilog
  • Appendix: Design Methodology
  • Appendix: HDL Coding Techniques

Day 6

  • Full FPGA Design Flow Hands-on Project




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