Designing FPGAs Using the Vivado Design Suite 2

This course shows you how to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Training Duration

2 days

Who Should Attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

Software Tools

  • Vivado System Edition 2016.3

Hardware

  • Architecture: UltraScale™ and 7 series FPGAs*
  • Demo board (optional): Kintex®-7 FPGA KC705 board*

Skills Gained

After completing this comprehensive training, you will know how to:

  • Create a Tcl script to create a project, add sources, and implement a design
  • Describe and use the clock resources in a design
  • Build resets into your system for optimum reliability and design speed
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Use the Vivado IP integrator to create a block design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Describe the HLx design flow that increases productivity
  • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

 

Course Outline 

 

Day 1

1.1 UltraFast Design Methodology Introduction

Overview of the methodology guidelines covered in this course.

 

1.2 Scripting in Vivado Design Suite Project Mode

Explains how to write Tcl commands in the project-based flow for a design.

1.3 Clocking Resources

Describes various clock resources, clocking layout, and routing in a design.

1.4 Synchronous Design Techniques

Introduces synchronous design techniques used in an FPGA design.

 

1.5 Register Duplication

Use register duplication to reduce high fanout nets in a design.

1.6 Resets

Investigates the impact of using asynchronous resets in a design.

 

1.7 I/O Logic Resources

Overview of I/O resources and the IOB property for timing closure.

1.8 Timing Summary Report

Use the post-implementation timing summary report to sign-off criteria for timing closure.

 

1.9 Generated Clocks

Use the report clock networks report to determine if there are any generated clocks in a design.

1.10 Clock Group Constraints

Apply clock group constraints for asynchronous clock domains.

1.11 Introduction to Timing Exceptions

Introduces timing exception constraints and applying them to fine tune design timing.

 

Day 2


2.1 Creating and Packaging Custom IP

    Create your own IP and package and include it in the Vivado IP catalog.

 

2.2 Using an IP Container

Use a core container file as a single file representation for an IP.

2.3 Designing with IP Integrator

  Use the Vivado IP integrator to create the uart_led subsystem.

2.4 Introduction to the HLx Design Flow

Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.


2.5 Configuration Process

     Understand the FPGA configuration process, such as device power up, CRC check, etc.

 

2.6 Sampling and Capturing Data in Multiple Clock Domains

Overview of debugging a design with multiple clock domains that require multiple ILAs.

2.7 Design Analysis Using Tcl Commands

Analyze a design using Tcl commands.

2.8 Power Analysis and Optimization Using the Vivado Design Suite

Use report power commands to estimate power consumption.

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