Designing with VHDL

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience. 
Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level

FPGA 1 

Training Duration

3 days

Who Should Attend

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

Prerequisites

  • Basic digital design knowledge

Software Tools

  • Vivado® Design or System Editon 2017.1

Hardware

  • Architecture: N/A*
  • Demo board: Kintex® UltraScale™ FPGA KCU105 or Kintex-7 FPGA KC705 board*

Skills Gained

After completing this training, you will know how to:

  • Implement the VHDL portion of coding for synthesis
    • Identify the differences between behavioral and structural coding styles
    • Distinguish coding for synthesis versus coding for simulation
    • Use scalar and composite data types to represent information
    • Use concurrent and sequential control structure to regulate information flow
    • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)
  • Simulate a basic VHDL design
    • Write a VHDL testbench and identify simulation-only constructs
  • Identify and implement coding best practices
    • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA
  • Create and manage designs within the Vivado Design Suite environment 

Course Outline

Day 1

1.1 The "Shape" of VHDL

1.2 Demo: Multiplexer

 1.3 Lab 1: Using the Tools

1.4 Data Types

1.5 Concurrent Operations

1.6 Lab 2: Using Concurrent Statements

1.7 Processes and Variables

1.8 Lab 3: Designing a Simple Process

Day 2

2.1 Introduction to Testbenches

2.2 Vivado Simulator Basics

2.3 Lab 4: Simulating a Simple Design

2.4 Creating Memory

2.5 Lab 5: Building a Dual-Port Memory

2.6 Finite State Machines

2.7 Lab 6: Building a Moore Finite State Machine

2.8 Targeting Xilinx FPGAs

2.9 Lab 7: Xilinx Tool Flow

Day 3

3.1 Loops and Conditional Elaboration

3.2 Lab 8: Using Loops

3.3 Attributes

3.4 Functions and Procedures

3.5 Packages and Libraries

3.6 Lab 9: Building Your Own Package

3.7 Interacting with the Simulation

3.8 Writing a Good Testbench

3.9 Lab 10: Building a Meaningful Testbench

  

DOWNLOAD REGISTRATION FORM

 

  ONLINE REGISTRATION

 

 

 

 

Course Registration Form


Course Title
Invalid Input

or Key in Your Own Title
Invalid Input

Course Start Date

Invalid Input

Sponsorship (*)
Invalid Input


Contact Person


Salutation(*)
Invalid Input

Name(*)
Invalid Input

Designation/ Department/ Division(*)
Invalid Input

Company(*)
Invalid Input

Billing Address (*)
Invalid Input

Street Address

(*)
Invalid Input

Street Address Line 2

City(*)
Invalid Input

State / Province(*)
Invalid Input

Postal / Zip Code(*)
Invalid Input

Telephone(*)
Invalid Input

Fax
Invalid Input

Email Address (*)
Invalid Input


Participant Details


Participant Salution 1
Invalid Input

Participant Name1
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 2
Invalid Input

Participant Name2
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 3
Invalid Input

Participant Name 3
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Payment Method(*)
Invalid Input

Cheque number
Invalid Input

PO Number
Invalid Input

How did you get to know about this programme?(*)
Invalid Input

Terms and Conditions
Invalid Input

Invalid Input