Embedded Systems Design

This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado® Design Suite. The features and capabilities of both the Zynq® All Programmable System on a Chip (SoC) and the MicroBlaze™ soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.

The Xilinx Zynq All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.

Level

Embedded Hardware 3 

Training Duration

2 days

Who Should Attend?

Engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC or MicroBlaze soft processor core using the Embedded Development Kit.

Prerequisites

  • FPGA design experience

  • Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado ® software implementation tools

  • Basic understanding of C programming

  • Basic understanding of microprocessors

  • Some HDL modeling experience

Software Tools

  • Vivado Design or System Edition 2016.3

Hardware

  • Architecture: Zynq-7000 All Programmable SoC (Cortex Tm-A9 processor) and MicroBlaze processor*

  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the various tools that encompass a Xilinx embedded design

  • Rapidly architect an embedded system containing a MicroBlaze™ or Cortex™-A9 processor by using the Vivado IP Integrator and Customization Wizard

  • Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)

  • Create and integrate an IP-based processing system component in the Vivado Design Suite

  • Design and add a custom AXI interface-based peripheral to the embedded processing system

  • Simulate a custom AXI interface-based peripheral using a bus functional model (BFM)

Course Outline

Day 1

1.1 Embedded UltraFast Design Methodology
Outlines the different elements that comprise the Embedded Design Methodology.
1.2 Overview of Embedded Hardware Development
Overview of the embedded hardware development flow.
1.3 Driving the IP Integrator Tool
Describes how to access and effectively use the IPI tool.
1.4 Overview of Embedded Software Development
Reviews the process of building a user application.
1.5 Driving the SDK Tool
Introduces the basic behaviors required to drive the SDK tool to generate a debuggable C/C++ application.
1.6 AXI: Introduction
Introduces the AXI protocol.
1.7 AXI: Variations
Describes the differences and similarities among the three primary AXI variations.
1.8 AXI: Transactions
Describes different types of AXI transactions.
1.9 Introduction to Interrupts
Introduces the concept of interrupts, basic terminology, and generic implementation.
1.10 Interrupts: Hardware Architecture and Support
Reviews the hardware that is typically available to help implement and manage interrupts.

Day 2

2.1 AXI: Connecting AXI IP
Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies.
2.2 Using the Create and Import Wizard to Create a New AXI IP
Explains how to use the Create and Import Wizard to create and package an AXI IP.
2.3 AXI: BFM Simulation
Describes how to perform BFM simulation, which can accelerate the pace of verification.
2.4 MicroBlaze Processor Architecture Overview
Overview of the MicroBlaze microprocessor architecture.
2.5 MicroBlaze Processor Block Memory Usage
Highlights how block RAM can be used with the MicroBlaze processor.  
2.6 Zynq-7000 All Programmable SoC Architecture Overview
Overview of the Zynq-7000 All Programmable SoC architecture.
2.7 Zynq UltraScale+ MPSoC Architecture Overview
Overview of the Zynq UltraScale+ MPSoC architecture.

 

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