Essential DSP Implementation Techniques for Xilinx FPGAs

This course provides a foundation for Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a refresher of basic binary number theory, mathematics, and the essential features within the FPGA that are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FFTs, video, and image processing. Throughout the course, Xilinx cores and IP relevant to signal processing are introduced. The course is complemented by hands-on exercises to reinforce the concepts learned.

Training Duration
2 Days

Who Should Attend?
Engineers and designers who have an interest in developing products that use digital signal processing.

Prerequisites

•A fundamental understanding of digital signal processing theory, including an understanding of the following principles

  • Sample rates
  • Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters
  • Oscillators and mixers
  • Fast Fourier Transform (FFT) algorithm

Recommended

Essentials of FPGA Design course

Hardware
•Architecture: 7 series FPGAs*
•Demo board: None*

Skill Gained
After completing this comprehensive training, you will know how to:

  • Describe the advantages of using FPGAs over traditional processors for DSP designs
  • Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
  • Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
  • Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
  • Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
  • Explain the algorithms for video and imaging systems and their implementations in FPGAs

 

Course Outline

Day 1

1.1 Back to Basics

1.2 Architecture

1.3 FPGA Math

1.4 Lab 1: Signed Number Conversion, Quantization and Rounding, Adders, Subtractors, and Accumulation
Learn how to estimate device resource utilization for basic math functions. Compare different methodologies for implementing functions.  

1.5 Shift Registers, RAM, and Applications

1.6 Lab 2: SRL32E and RAM Estimation and Concatenation
Learn how to optimize memory and storage in Xilinx FPGAs.  

1.7 FIR Filter

1.8 Lab 3: Filter Implementation, Resource and Performance Estimation
Learn how and when to use various implementation strategies for optimal filter implementation.

Day 2

2.1 Advanced Filter Techniques

2.2 Lab 4: Filter Implementations, Resource and Performance Estimation
Advanced filter topologies are studied. Architect multichannel and multirate filters using various methods. Implementation strategies will be discussed and optimal methods used.  
 
2.3 Fast Fourier Transform
 
2.4 Lab 5: FFT Implementation, Resource and Performance Estimation
Select correct parameters for FFT implementations to meet design targets. Resource estimation will be studied and trade-offs with performance examined through implementation examples.

2.5 Video and Imaging

2.6 Where Do We Go From Here?

2.7 Demonstration: System Generator and the CORE Generator Tool with a DSP-Targeted Reference Design
Targeted Reference Design – Introduces DSP-targeted hardware boards and software tools. Witness the power, ease of use, and design efficiency of Xilinx DSP tools and IP. Reinforce the concepts studied in the course material and exercises.  
 
2.8 Where Can I Learn More?

 

DOWNLOAD REGISTRATION FORM

   ONLINE REGISTRATION

 

 

 

Course Registration Form


Course Title
Invalid Input

or Key in Your Own Title
Invalid Input

Course Start Date

Invalid Input

Sponsorship (*)
Invalid Input


Contact Person


Salutation(*)
Invalid Input

Name(*)
Invalid Input

Designation/ Department/ Division(*)
Invalid Input

Company(*)
Invalid Input

Billing Address (*)
Invalid Input

Street Address

(*)
Invalid Input

Street Address Line 2

City(*)
Invalid Input

State / Province(*)
Invalid Input

Postal / Zip Code(*)
Invalid Input

Telephone(*)
Invalid Input

Fax
Invalid Input

Email Address (*)
Invalid Input


Participant Details


Participant Salution 1
Invalid Input

Participant Name1
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 2
Invalid Input

Participant Name2
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 3
Invalid Input

Participant Name 3
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Payment Method(*)
Invalid Input

Cheque number
Invalid Input

PO Number
Invalid Input

How did you get to know about this programme?(*)
Invalid Input

Terms and Conditions
Invalid Input

Invalid Input