Free Workshop: Xilinx

Best FPGA Design Practices and Methodology and High Level Design Techniques with HLS/SDSoC

Workshop Objectives

 

This half-day workshop will share with you practical and proven ways to design your FPGA based systems faster.  Hear from our Master Trainer the latest technologies to effectively design and realise your systems.   Uncover new techniques and best practices in board planning, design creation, IP integration, design implementation and closure techniques, programming and hardware debug practiced by leading FPGA engineers worldwide.

Topics covered

 

 

 

UltraFast Design Methodology

 

 

 

Introduces the best practices to enable efficient design closure with fewer iterations. Vivado is a powerful Design Environment and user may follow habitual inefficient design practices that can lead to longer design cycles. UltraFast is the collection of best practices compiled from global teams and recommended by Xilinx.

 

 

 

Moving Higher - Abstractions for Xilinx Platforms

 

 

 

With complex and powerful design platforms, it is increasingly necessary to use High Level Design methodologies that enable shorter concept-to-design cycles. These include High Level Synthesis (HLS) of C/C++ algorithm to hardware, SDSoC tools that are extensively automated to compile bottle necks of software based algorithms into Programmable Logic fabric, without the software engineer having to understand the details of hardware design.

 


Limited Seats, Register Now

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