Free Workshop: MATLAB & Xilinx

Xilinx FPGA and Zynq SOC Design using MATLAB and SIMULINK

Workshop Objectives

 

This half-day workshop focuses on providing overview of Xilinx FPGA and Zynq SOC design using MATLAB and SIMULINK. Automatic HDL code generation and verification on different levels of abstraction to accelerate the FPGA and Zynq SOC design workflow will be elaborated.

Course Outline

 

Introduction to MATLAB and SIMULINK

 

• Overview of MATLAB and SIMULINK environment

 

Zynq Platform Overview and Environment Setup

 

• Configure Zynq-7000 platform and MATLAB environment

 

• Testing connectivity to Zynq Hardware

 

Introduction to Embedded Coder and HDL Coder

 

• Configure Simulink models for embedded code generation

 

• Using HDL Workflow Advisor for HDL code generation

 

IP Core Generation and Deployment

 

• Use HDL Workflow Advisor to configure a Simulink model

 

• Generate and build both HDL code for the Xilinx

 

FPGA and C code for Zynq SOC

 

• Deploy to Zynq platform

 


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