What’s the difference between VHDL & Verilog? - Lee Choon Lin

This is a common question asked when beginner is looking at which HDL language to learn.  I am well-versed in both languages, although I started as a Verilog user for 10 years.  In short, here' some quick points to note: 

VHDL is the first HDL(Hardware Description Language), which is developed since year 1980. After four years, Verilog was created by Prabhu Goel and Phil Moorby during winter of 1984.

VHDL

Verilog

Advanced features in Functionality Verification

Need to spend more efforts on creating advanced testbench (Functionality Verification

EUROPEAN company prefer VHDL

US Company prefer Verilog

Complex Syntax – Slow coding

Simple Syntax- Easy to pick up, Fast coding

Supported in Synthesis tool – Netlist

Supported in Synthesis Tool - Netlist

 

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